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Method and device for frequency synthesis using a phase locked loop

申请公布号:US2002149430(A1)

申请号:US20020069444

申请日期:2002.05.22

申请公布日期:2002.10.17

申请人:
BRUNET ARNAUD;RIEUBON SEBASTIEN

发明人:BRUNET ARNAUD;RIEUBON SEBASTIEN

分类号:H03L7/089;H03L7/197;(IPC1-7):H03L7/00

主分类号:H03L7/089

摘要:The present invention relates to a frequency synthesis system and device using a phase locked loop. A frequency synthesis method using a phase locked loop including a phase comparator, said method including a step of switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of said loop has elapsed, which method is characterized in that it consists of effecting said operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).

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