Efficient implementation of error correction code scheme

申请公布号：US2002120890(A1)

申请号：US20010792533

申请日期：2001.02.23

申请公布日期：2002.08.29

申请人：

INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人：CALVIGNAC JEAN LOUIS;HEDDES MARCO C.;LOGAN JOSEPH FRANKLIN;VERPLANKEN FABRICE JEAN

分类号：G06F11/00;G06F11/10;G11C29/00;H03M13/00;(IPC1-7):G11C29/00

主分类号：G06F11/00

摘要：A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

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