Boundary scan test cell circuit

申请公布号：US2001047499(A1)

申请号：US20010898249

申请日期：2001.07.03

申请公布日期：2001.11.29

申请人：

WHETSEL LEE D.

发明人：WHETSEL LEE D.

分类号：G01R31/28;G01R31/3185;G06F19/00;(IPC1-7):G01R31/28

主分类号：G01R31/28

摘要：A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-Flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

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