BUS CONTROL SYSTEM FOR INTEGRATED CIRCUIT DEVICE IMPROVED IN BUS TREE EFFICIENCY,申请号KR20010001247-传众专利搜索

BUS CONTROL SYSTEM FOR INTEGRATED CIRCUIT DEVICE IMPROVED IN BUS TREE EFFICIENCY

申请公布号：KR20010076242(A)

申请号：KR20010001247

申请日期：2001.01.10

申请公布日期：2001.08.11

申请人：

FUJITSU LIMITED

发明人：HIROSE YOSHIO;SARUWATARI TOSHIAKI;UTSUMI HIROYUKI

分类号：G06F13/36;G06F9/38;G06F13/12;G06F13/28;(IPC1-7):G06F13/36

主分类号：G06F13/36

摘要：PURPOSE: To enable the operation of a bus in a high speed frequency. CONSTITUTION: An issue side LSI has a counter, to which a value showing how many commands can be simultaneously processed by a receiving side LSI or how many pieces of data can be simultaneously received is loaded at the time of initialization and when issuing a command or data, the counter is decremented. When a ready signal is received, the counter is incremented and when the counter is turned to '0', the issue of the command or data is suppressed. Therefore, the issue side LSI can issue the command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI. Since the command or data issue side LSI can manage the state of the command buffer or data buffer of the receiving side LSI, even when the bus is operated at high speed, the command or data can be efficiently issued.