Multi-level instruction cache for a computer,申请号US19960768417-传众专利搜索

Multi-level instruction cache for a computer

申请公布号：US5860096(A)

申请号：US19960768417

申请日期：1996.12.18

申请公布日期：1999.01.12

申请人：

HEWLETT-PACKARD COMPANY

发明人：UNDY, STEPHEN R.;KNEBEL, PATRICK;GLEASON, CRAIG A.

分类号：G06F9/38;G06F12/08;(IPC1-7):G06F12/08

主分类号：G06F9/38

摘要：A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.