SYSTEM FOR ANALYZING AND DISPLAYING DEFECTIVE MEMORY,申请号JP19970126489-传众专利搜索

SYSTEM FOR ANALYZING AND DISPLAYING DEFECTIVE MEMORY

申请公布号：JPH10308099(A)

申请号：JP19970126489

申请日期：1997.04.30

申请公布日期：1998.11.17

申请人：

HITACHI CHIYOU LSI SYST:KK

发明人：HAYASHI HIDEKI;YOSHIDA MASAHIRO

分类号：G11C29/44;G11C29/00;(IPC1-7):G11C29/00

主分类号：G11C29/44

摘要：PROBLEM TO BE SOLVED: To disclose defective information such as a fail bit map and the like by simple operation. SOLUTION: An analyzing and displaying system for a defective memory performs operation taking a probing test result of a semiconductor memory accomplished on a semiconductor wafer, operation performing cutting of defective information, operation converting defective information of a memory cell to address information of two dimension and making it as a picture file of a file bit map, and operation making a display control instruction displaying a picture file as a character file. This system is provided with a file server 3 receiving and storing a picture file and a character file made by an analyzing device 2 for a defective memory through a network 5, a display device 4 displaying graphics and characters, and an input/output device controlling display operation, specifies a picture file or a character file to be displayed to the file sever 3 through the network 5 and displays it on a display screen of the display device 4.