LOGIC SIMULATION METHOD,申请号JP19940153735-传众专利搜索

LOGIC SIMULATION METHOD

申请公布号：JPH0815385(A)

申请号：JP19940153735

申请日期：1994.07.05

申请公布日期：1996.01.19

申请人：

SANYO ELECTRIC CO LTD

发明人：MATSUMOTO YUKINORI

分类号：G01R31/28;G06F17/00;G06F17/50;G06F19/00;(IPC1-7):G01R31/28

主分类号：G01R31/28

摘要：<p>PURPOSE:To realize a high speed correct simulation by processing an objective event taken out from a slot of time wheel and updating the processed even number. CONSTITUTION:Upon generation of an event, a sequential number representative of the order of generation is affixed to the event and the processed even number is recorded as the data of each element. An event 13 is then taken out from the slot 11 of a time wheel 1 and the processed event number is compared with the sequential number. The event 13 is processed only when the sequential number is higher. The output value is also calculated and updated simultaneously with the processed event number and a new event is registered in the slot 11. For a plurality of registered events generated simultaneously on a same signal line, only the last event is processed. Consequently, the last event has a correct signal value. This method enhances the processing speed of simulation through single path processing only of effective event while avoiding erroneous processing of event.</p>