Design for testability technique of CMOS and BiCMOS ICs.,申请号EP19940830023-传众专利搜索

Design for testability technique of CMOS and BiCMOS ICs.

申请公布号：EP0664512(A1)

申请号：EP19940830023

申请日期：1994.01.24

申请公布日期：1995.07.26

申请人：

STMICROELECTRONICS S.R.L.

发明人：PENZA LUIGI;FAVALLI MICHELE;RICCO' BRUNO

分类号：G01R31/26;G01R31/28;G01R31/30;G01R31/317;H01L21/66

主分类号：G01R31/26

摘要：A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected BICSs avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional IDDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node (shadow line) and a supply rail of the IC. <IMAGE> <IMAGE>