Method and apparatus for parallel testing of memory.,申请号EP19940304644-传众专利搜索

Method and apparatus for parallel testing of memory.

申请公布号：EP0634751(A1)

申请号：EP19940304644

申请日期：1994.06.27

申请公布日期：1995.01.18

申请人：

STMICROELECTRONICS, INC.

发明人：MCCLURE, DAVID CHARLES

分类号：G11C29/00;G11C29/12;G11C29/28

主分类号：G11C29/00

摘要：A memory includes a number of memory groups. Each memory group includes a set of memory subgroups and a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output. The true and complement inputs are connected to a memory subgroup by at least one sense amplifier. A true connection point also is included in the memory, and the true output of one of the data bus drivers from each of the memory groups are connected together at the connection point, and a "wired" configuration is created. In addition, the memory includes a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the connection point, creating a "wired" configuration. The memory also has a data bus circuit with a true input connected to the true connection point and a complement input connected to the complement connection point and a first circuit. This data bus circuit is responsive to signals from the true and complement connection points created by the simultaneous addressing of multiple groups or a subset of the memory subgroups in testing mode. The first circuit has an output for providing an indication of an error in addressing of the multiple groups or the subset of the memory subgroups. <IMAGE>