SAMPLE RATE CONVERSION CIRCUIT,申请号JP19900251556-传众专利搜索

SAMPLE RATE CONVERSION CIRCUIT

申请公布号：JPH04129413(A)

申请号：JP19900251556

申请日期：1990.09.20

申请公布日期：1992.04.30

申请人：

SONY CORP

发明人：TOKUHARA MASAHARU;WATANABE KAZUO;TODO HIROBUMI

分类号：H04N19/00;H03H17/00;H03H17/02;H04N11/04;H04N19/42;H04N19/59;H04N19/80;H04N19/85

主分类号：H04N19/00

摘要：<p>PURPOSE:To realize a sample rate conversion circuit whose circuit scale is reduced by using a multiplier in common for the processing of plural digital data. CONSTITUTION:The circuit is provided with plural 1st latch means 1a latching plural digital data at a 1st sampling clock respectively and plural 2nd latch means 2a latching again each digital data latched by each 1st latch means 1a at a 2nd sampling clock respectively. Then a digital data latched by each of the 2nd latch means 2a is outputted selectively to multipliers M0-Mn at a prescribed order with selection means SW0-SWn and the resulting data is extracted as a time division multiplex data. Since the processing of plural digital data is implemented by the multipliers M0-Mn in common and number of the multipliers M0-Mn with a highest circuit scale is reduced. Thus, the entire circuit is reduced.</p>