CHATTERING ELIMINATION CIRCUIT,申请号JP19900212045-传众专利搜索

CHATTERING ELIMINATION CIRCUIT

申请公布号：JPH0494211(A)

申请号：JP19900212045

申请日期：1990.08.09

申请公布日期：1992.03.26

申请人：

SHARP CORP

发明人：GOTO ATSUSHI;TADA JUNJI

分类号：H03K5/1254;H03K5/01

主分类号：H03K5/1254

摘要：PURPOSE:To eliminate chattering of an input signal completely and to facilitate circuit integration by using an AND gate, a NOR gate and a JK flip-flop and devising an output signal not to be switched except for the case that all plural parallel signals are at a high level or a low level. CONSTITUTION:D flip-flops 6-8 of a 3-bit shift register 1 generate parallel output signals S3-S5 resulting from deviating a phase of an input signal S2 by a drive period of a drive clock signal S1 respectively from output terminals 1Q-3Q. An AND gate 2 outputs a high level signal to a J input terminal of a JK flip- flop 4 only when the parallel output signals S3-S5 are all at a high level signal. On the other hand, a NOR gate 3 outputs a high level signal to a K input terminal of the JK flip-flop 4 only when the parallel output signals S3-S5 are all at a low level signal. Thus, fluctuation included in the input signal S2 due to chattering is eliminated and the circuit is easily realized by an IC.