Memory structure for nonsequential storage of block bytes in multi bit chips

申请公布号：US4992979(A)

申请号：US19880231813

申请日期：1988.08.12

申请公布日期：1991.02.12

申请人：

INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人：AICHELMAN, JR., FREDERICK J.;SOLLITTO, JR., VINCENT F.

分类号：G06F11/10;G06F12/04;G11C7/10

主分类号：G06F11/10

摘要：A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

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