DELAY CIRCUIT
申请公布号:JPH01225220(A)
申请号:JP19880051045
申请日期:1988.03.03
申请公布日期:1989.09.08
发明人:HIRASAWA MASAO
分类号:H03K5/13;H03K5/133
主分类号:H03K5/13
摘要:PURPOSE:To absorb the dislocation of a delay time, which is generated by the variance of a condition on a process, etc., by providing plural delay means, whose delay times are different, and selecting the outputs of these delay means with a selecting instruction. CONSTITUTION:A delay circuit 1 is composed of delay circuits 2-4, a selecting register 5 and a selecting circuit 6. The delay circuits 2-4 are serially connected and the outputs of the respective delay circuits 2-4 are inputted to the selecting circuit 6 and the selecting instruction is given to the selecting register 5 and based on the output of this selecting register 5, the outputs of the delay circuits 2-4 are selected and outputted by the selecting circuit 6.
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