Virtual memory arrangement data processing system with decoding and execution of prefetched instructions in parallel,申请号US19870030021-传众专利搜索

Virtual memory arrangement data processing system with decoding and execution of prefetched instructions in parallel

申请公布号：US4847748(A)

申请号：US19870030021

申请日期：1987.03.25

申请公布日期：1989.07.11

申请人：

NEC CORPORATION

发明人：YAMAHATA, HITOSHI;SATO, YOSHIKUNI

分类号：G06F9/38

主分类号：G06F9/38

摘要：A data processing system comprises: an instruction queue memory; an instruction decode unit; an address computation unit; an address translation unit; and an instruction execution unit. Further comprised is a decoded instruction queue memory having a queue structure composed of a plurality of entries for latching an entry information. The decoded instruction queue memory includes: a first counter adapted to be counted up in response to the effective address computation requiring signal of the instruction decode unit and down in response to the translation completion signal of the address translation unit; and a second counter having a counting-down function. When the first and second counters are to be counted down, one closer to the instruction execution unit and having a counted value other than zero is counted down. When the queue is the decoded instruction queue memory advances, the first counter has its counted value copied to that of the second counter and then set at the value of zero. The instruction decode unit can execute the instruction decoding and execution in parallel, and a decoding, an effective address computation and an address translation of the decoded instruction in parallel, thereby to shorten the decoding time period.