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MICROCOMPUTER SYSTEM

申请公布号:JPS63240631(A)

申请号:JP19870074921

申请日期:1987.03.27

申请公布日期:1988.10.06

申请人:
NEC CORP

发明人:MITA KOJI

分类号:G06F9/34;G06F9/38;G06F12/06;G06F15/78

主分类号:G06F9/34

摘要:<p>PURPOSE:To shorten an instruction code fetching cycle and to suppress the generation of a bus neck by securing such a mechanism where a microprocessor gives the direct control to a memory chip set on a single semiconductor substrate and performs a close coupling action. CONSTITUTION:A microcomputer system consists of a microprocessor 100, an instruction pointer IP, a data pointer DP, an incrementer/decrementer 101-5, and a memory chip 101 containing a memory 101-1 set on a semiconductor substrate. The processor 100 controls the update timing of both pointers IP and DP of the chip 101 so that the instruction codes can be continuously read out of the memory 101-1 with no output of the address of a fetching destination of the instruction code. Thus, the stack working speed is increased. In such a way, an instruction code fetching cycle is shortened and the generation of a bus neck can be suppressed.</p>

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