INTERFACE CIRCUITRY FOR COMMUNICATING BY MEANS OF MESSAGES
申请公布号:ZA8703067(B)
申请号:ZA19870003067
申请日期:1987.04.29
申请公布日期:1987.12.30
发明人:GUIDO REMI MARCEL GALLOPYN
分类号:G05B;G06F3/00;G06F13/00;H03K
主分类号:G05B
摘要:Two buffer circuits of FIFO type, connected together in anti-parallel mode, form a bi-directional message buffer. Communications between the processors is via data busses and input/output circuits. The unit contains two status registers and two command registers. Each status register operates on 8-bit words, the first bit of which indicates whether a message from its associated processor is available. Each command register operates on an 8-bit word. the second bit of which indicates that a meassage has been received. When the message received bit is set it automatically resets the message available bit in the status register.
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