SEMICONDUCTOR DEVICE
申请公布号:JPS61268034(A)
申请号:JP19850111430
申请日期:1985.05.22
申请公布日期:1986.11.27
发明人:KUROHICHI MINORU;SHINKAWA TANEKAZU;IWAMORI KIYOSHI
分类号:G01R31/26;H01L21/66;H01L21/822;H01L27/04
主分类号:G01R31/26
摘要:PURPOSE:To remove an element chip, the withstanding voltage of a gate oxide film therein is low due to a defect, etc. on manufacture, at the step of a wafer test before the element chip is transferred to an assembly process regarding the element chip by forming element-chip structure capable of conducting a burn-in test under the state of a semiconductor wafer. CONSTITUTION:All of each input terminal pad 1 are connected in common by a polysilicon wiring 3 through fuses 2 for limiting overcurrents, and the polysilicon wiring 3 is connected to pads 4 for fusion-cutting several fuse. A power-supply terminal pad 5 and a GND terminal pad 6 are connected to each of these pads 4 for fusion-cutting through the fuses 2 for limiting overcurrents. High-concentration P-type diffusion layers 7 are formed to the lower layers of the pads 4 for fusion-cutting the fuses while each of the high-concentration P-type diffusion layers 7 is arranged to a dicing line 11 for the whole, and GNDs for several chip are made common. Accordingly, a burn-in test can be conducted under the state of a wafer, thus removing element chips, which will be formed as defectives at an initial stage, before assembly by the burn-in test.
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