Dynamic memory circuit with improved noise-prevention circuit arrangement for word lines,申请号US19830546759-传众专利搜索

Dynamic memory circuit with improved noise-prevention circuit arrangement for word lines

申请公布号：US4610002(A)

申请号：US19830546759

申请日期：1983.10.28

申请公布日期：1986.09.02

申请人：

NEC CORPORATION

发明人：KANEKO, SHOUJI

分类号：G11C11/413;G11C8/08;G11C8/10;(IPC1-7):G11C11/40;G11C13/00

主分类号：G11C11/413

摘要：A memory circuit provided with improved noise-prevention circuit arrangement for word lines is disclosed. The memory circuit is structured in such a manner that each word decoder is provided for each word line group including a plurality of word lines for selecting the associated word line group, and a noise-prevention circuit of a flip flop type is provided for each of the work decoder for preventing an output of the word decoder from floating when that word decoder is not selected.