EXPANSION PROCESSING CIRCUIT,申请号JP19840103032-传众专利搜索

EXPANSION PROCESSING CIRCUIT

申请公布号：JPS60247333(A)

申请号：JP19840103032

申请日期：1984.05.22

申请公布日期：1985.12.07

申请人：

TOSHIBA KK;TOUSHIBA AUDIO BIDEO ENGINEERING KK

发明人：MIYAGUCHI YUTAKA;IKEDA YUKIHISA

分类号：H03M7/50;H04B14/04

主分类号：H03M7/50

摘要：PURPOSE:To improve the resistance to repetition of the analog/digital and digital/analog conversions in a dubbing mode and to reduce the deterioration in S/N and a distortion factor with record and reproduction outputs, by securing the optimum key value in an expansion mode. CONSTITUTION:The reproduced 8-bit data received an error correction is supplied through an input terminal 11 in the form of parallel data. In this case, the higher 5 bits of the data are supplied to a rank deciding circuit 12. The circuit 12 discriminates ranks according to the information on these bits and transmits the control signals to an adder circuit 13 and a control circuit 14. The circuit 13 substracts the corrected number applied in a compression mode from the input data; while the circuit 14 controls switches SW1-SW10 according to the control signal given from the circuit 12 and adds the omitted bits to obtain again the digital data of 10 bits. In this case, the MSB of a bit train to be added is set at ''1'' with the bits smaller than ''1'' set at ''0''. Thus the key value of a ''group'' is set at the carry value closest to the mean value of said ''group''.