Method of and circuit arrangement for reading an integrated semiconductor store with storage cells in MTL (I2L) technology,申请号US19820414122-传众专利搜索

Method of and circuit arrangement for reading an integrated semiconductor store with storage cells in MTL (I2L) technology

申请公布号：US4521873(A)

申请号：US19820414122

申请日期：1982.09.02

申请公布日期：1985.06.04

申请人：

INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人：HEUBER, KLAUS;WIEDMANN, SIEGFRIED K.

分类号：G11C11/414;G11C11/416;(IPC1-7):G11C7/00

主分类号：G11C11/414

摘要：A method of and a circuit arrangement for reading an integrated MTL(I2L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant ( tau e) of the bit line PNP transistor (T4) connected to the switched "OFF" NPN transistor (T3) of a cell. The effective storage time constant ( tau SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant ( tau e). As a result of the different time constants ( tau e and tau SAT), the two storage charges (Q1 and Q4) are discharged at different rates during the third phase (t3), thus generating a very fast and high output signal ( DELTA VBL=VS).