SECOND ORDER DELTA SIGMA MODULATOR
申请公布号:JPS6031315(A)
申请号:JP19830139023
申请日期:1983.07.29
申请公布日期:1985.02.18
发明人:MARUTA RIKIO
分类号:H03M3/02;(IPC1-7):H03M3/02
主分类号:H03M3/02
摘要:PURPOSE:To attain low power consumption, low cost and miniaturization of a DELTASIGMA modulator itself by means of large circuit integration by constituting circuit components requiring highly accurate operation to an analog signal such as generation of an approximate signal, differential calculation between an input signal or a first stage integration signal and the approximate signal and integration calculation or the like with an operational amplifier, a capacitor and a switch. CONSTITUTION:An input analog signal is given to a terminal 501, a reference voltage is given to a terminal 502, the 1st clock pulse phi1 is given to a terminal 503 and the 2nd clock pulse phi2 is given to a terminal 504 and a DELTASIGMA code is outputted at a terminal 505. The 1st approximate signal is formed by the combination of the 2nd switched capacitor circuit and the 3rd switched capacitor circuit, and the 2nd approximate signal is formed by the combination of the 5th switched capacitor circuit and the 6th switched capacitor circuit. Since an inverting input of an operational amplifier 540 becomes an imaginary grounding point because of the negative feedback by a capacitor C4 and its potential is 0, a current to discharge an electric charge V(t1).C1 stored in a capacitor C1 to 0 flows through the conduction of S2 switches 513, 514.
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