Semiconductor memory circuit

申请公布号：US4402066(A)

申请号：US19810234716

申请日期：1981.02.17

申请公布日期：1983.08.30

申请人：

FUJITSU LIMITED

发明人：ITOH, HIDEO;SHIMADA, HIROSHI

分类号：G11C11/41;G11C7/10;G11C11/417;G11C11/419;(IPC1-7):G11C7/00

主分类号：G11C11/41

摘要：A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.

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