CONTROLLING SYSTEM FOR MEMORY WRITING PULSE,申请号JP19810156446-传众专利搜索

CONTROLLING SYSTEM FOR MEMORY WRITING PULSE

申请公布号：JPS5857687(A)

申请号：JP19810156446

申请日期：1981.09.30

申请公布日期：1983.04.05

申请人：

FUJITSU KK

发明人：FUJINO MITOO;TATEISHI TERUTAKA

分类号：G06F12/16;G06F12/00;G11C29/04

主分类号：G06F12/16

摘要：PURPOSE:To simplify the observation for the time relation between the writing pulse and each register output, by repeating the writing action with a single unit of a memory device and at the same time setting 1 and 0 alternately to an address register and a writing data register. CONSTITUTION:The logic 1 is fed to an input terminal 1 for the timing control of the writing pulse; while the logic 0 is fed to the terminal 1 when no timing control is carried out. A selecting circuit has no working when the logic 0 is fed to the terminal 1. Thus the input signal of side (a) is selected. A timing control circuit 2 is driven by the signal which is set to a latch L1, and a writing pulse 4 is produced from the output of a prescribed stage and via a delaying circuit 7. Then the prescribed data is written to a prescribed address of a memory device 3.