GATE ARRAY INTEGRATED CIRCUIT,申请号JP19840120802-传众专利搜索

GATE ARRAY INTEGRATED CIRCUIT

申请公布号：JPS611044(A)

申请号：JP19840120802

申请日期：1984.06.14

申请公布日期：1986.01.07

申请人：

TOSHIBA KK

发明人：YAMADA MASAAKI

分类号：H01L21/822;H01L21/82;H01L27/04;H01L27/118

主分类号：H01L21/822

摘要：PURPOSE:To reduce the size of a chip by forming transistors of different current drives at the center and the both ends of a logic gate row to form the array of logic gates, thereby effectively utilizing the space. CONSTITUTION:Gates 31 having small size are arranged at the center of a gate array 2 on a chip 1, and gates 32 having large size are arranged at both ends. Since the gates at both ends are generally increased in the length of wirings to next stage, a large driving force is required, but necessary drive force can be obtained by relatively increasing the size. Since the length of the wirings of the gates at the center to the next stage is relatively short, a large drive force is not necessary, but may be formed of small size. When the gate array is thus formed, the width of the channel 4 at the center is large, and the channels 4 at both ends are shorter. When the gate array is wired, a trend of concentrating the wirings in a complicated manner occurs at the center of the channel. Accordingly, the wiring can be facilitated by increasing the width of the channel at the center, and the chip area can be efficiently utilized as a whole.