CHATTERING PREVENTING CIRCUIT,申请号JP19800057401-传众专利搜索

CHATTERING PREVENTING CIRCUIT

申请公布号：JPS56153835(A)

申请号：JP19800057401

申请日期：1980.04.30

申请公布日期：1981.11.28

申请人：

NIPPON ELECTRIC CO

发明人：NOZAKI TOSHIAKI

分类号：H03K5/1254;H03K17/00;H03K17/16

主分类号：H03K5/1254

摘要：PURPOSE:To secure an automatic priority for one of plural swtich signals, by giving difference to the phase of the clock which controls plural waveform shaping circuits and waveform delaying circuits that receive the signals of plural switches pushed simultaneously. CONSTITUTION:The outputs of operation swtiches SWS1 and SWS2 are supplied to the synchronous waveform shaping circuits 31 and 33 respectively, and the outputs Q31 and Q33 are supplied to the synchronous waveform delaying circuits 32 and 34 each. The outputs Q32 and Q34 of circuits 32 and 34 plus the outputs of NOTQ31 and Q33 of circuits 31 and 33 are supplied to the NOR circuits 37 and 38 that produce the synthetic signals. The circuits 31 and 33 operate with the fall of clock phi; and circuits 32 and 33 work with the rise of clock phi, respectively. The circuits 31 and 32 receive a supply of the clock phi via an inverter circuit 39. At the same time, the NOT outputs of circuits 31 and 32 are supplied to the NAND circuit 35, and the NOT outputs of circuits 33 and 34 are supplied to the NAND circuit 36. The outputs of circuit 35 and 36 are supplied to the circuits 28 and 37, respectively. In such constitution, only the output SII is set at H level although both SWS1 and SWS2 are pushed simultaneously.