LOGICAL SIMULATION METHOD AND LOGICAL SIMULATION DEVICE,申请号JP19880056615-传众专利搜索

LOGICAL SIMULATION METHOD AND LOGICAL SIMULATION DEVICE

申请公布号：JPH01230142(A)

申请号：JP19880056615

申请日期：1988.03.10

申请公布日期：1989.09.13

申请人：

MATSUSHITA ELECTRIC IND CO LTD

发明人：KANAZAWA YASUYUKI

分类号：G06F11/25;G06F17/50;G06F19/00

主分类号：G06F11/25

摘要：PURPOSE:To prevent the reduction of a simulation speed due to the fact that the present time is proceeded and a clearance can be formed at a pipeline without awaiting that the event is eliminated out of an event fetching part and a circuit action calculating part by adding an identifier, which is a color, to the event. CONSTITUTION:Plural colors are switched, a color is added to an event by a coloring part 4, the event in an event fetching part 3 and a circuit action calculating part 5 is color-coded, and by a notice color designating part 7, the coloring part 4 selects on color out of plural colors which can be added to the event and makes it into a notice color. An notice color existence deciding part 6 decides whether or not the event having the notice color exists in the event fetching part 3 and the circuit action calculating part 5, and by using the output of the notice color existence deciding part 6, the present time is proceeded according to the fact whether or not the event having the notice color exists in the circuit action calculating part 5. Thus, the clearance of the pipeline can be minimized and the higher speed can be obtained.