MEMORY CELL AND CORRESPONDING DEVICE,申请号US201615140023-传众专利搜索

MEMORY CELL AND CORRESPONDING DEVICE

申请公布号：US2017011808(A1)

申请号：US201615140023

申请日期：2016.04.27

申请公布日期：2017.01.12

申请人：

STMicroelectronics S.r.l.

发明人：Mirabella Ignazio Bruno;Pappalardo Salvatore;Ribellino Calogero;Nicolosi Alessandro

分类号：G11C17/18

主分类号：G11C17/18

地址：Agrate Brianza IT

摘要：A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

主权项：1. A memory cell, comprising: a plurality of storage elements for redundantly storing an input data logic signal, said plurality of storage elements having output lines for outputting a respective plurality of logic signals having respective logic values, a logic combination network sensitive to said respective logic values of said logic signals on said output lines, said logic combination network configured to generate an output signal of the cell having the same logic value as a majority of said logic signals on said output lines, and an exclusive logic sum circuit sensitive to said respective logic values of said logic signals on said output lines, said exclusive logic sum circuit configured to produce a refresh of said data logic signal as stored in said plurality of storage elements, said exclusive logic sum circuit activated when one of said logic signals on said output lines undergoes a logic value transition.