SEMICONDUCTOR MEMORY APPARATUS
申请公布号:JP2009252275(A)
申请号:JP20080097272
申请日期:2008.04.03
申请公布日期:2009.10.29
发明人:TAKAMI SHINYA
分类号:G11C16/06;G11C11/419
主分类号:G11C16/06
摘要:<p><P>PROBLEM TO BE SOLVED: To attain fast reading by a single-end sense amplifier, and reduce a circuit area and power consumption by dispensing with a dummy memory cell provided in a related technique. <P>SOLUTION: A semiconductor memory device includes a discharge circuit 102 that discharges bit lines to a ground potential, a sense amplifier 108 of a single-ended input configuration, and a charging transistor 106 connected between a power supply and an input node SAin of the sense amplifier. The charging transistor 106 charges a bit line from a side of the input node of the sense amplifier via the selected column select transistors (N0, N1, ...) which are set to on-states. When a current path to the ground from the bit line to which a selected memory cell is connected is turned off during reading, the input node of the sense amplifier is charged by the charging transistor 106, and a potential at the input node of the sense amplifier is thereby raised. After the input node of the sense amplifier has been further charged with the one of the column select transistors turned off, the reading operation is performed. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
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