DECODER AND DECODING METHOD
申请公布号:JP2001352258(A)
申请号:JP20000172681
申请日期:2000.06.08
申请公布日期:2001.12.21
发明人:MIYAUCHI TOSHIYUKI
分类号:G06F11/10;H03M13/45;(IPC1-7):H03M13/45
主分类号:G06F11/10
摘要:PROBLEM TO BE SOLVED: To realize high speed operation without deteriorating the performance by performing log-sum correction through linear approximation while attaching importance to the speed. SOLUTION: The decoder comprises a linear approximation circuit 68 for calculating a correction term being added to provide a logarithmic likelihood and represented by a one-dimensional formula for variables through linear approximation. The linear approximation circuit 68 represents a coefficient -a indicative of the inclination of a function F=-a|P-Q|+b and a coefficient b indicative of a segment using the power of 2 and calculates the correction term by performing log-sum correction through linear approximation. When the coefficient a is represented by -2-k and the coefficient b is represented by 2m-1, the approximation circuit 68 shifts the bits by rounding off the absolution value data|P-Q|from least significant 1 bit to least significant k bit and an inverter 91 inverts m bits from the least significant k+1 bit to least significant m+k bit.
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