Multilevel logic circuit with floating node voltage clamp,申请号US19870129106-传众专利搜索

Multilevel logic circuit with floating node voltage clamp

申请公布号：US4823028(A)

申请号：US19870129106

申请日期：1987.12.04

申请公布日期：1989.04.18

申请人：

TEKTRONIX, INC.

发明人：LLOYD, RANDALL B.

分类号：H03K3/012;H03K3/2885;(IPC1-7):H03K19/086;H03K17/16;H03K19/003;H03K19/092

主分类号：H03K3/012

摘要：A multilevel logic circuit includes a pair of resistors coupling collectors of an emitter-coupled pair of transistors to a voltage source, and includes a switch selectively connecting the emitters of the transistors to a current source. When the switch is closed, an input signal applied across the bases of the transistors controls an output signal produced between their collectors. When the switch is open, both transistors are off and the output signal is not affected by the input signal. A clamping circuit connected to a circuit node at the emitters of the transistors maintains a constant voltage at the node sufficient to prevent leakage current from charging or discharging inherent circuit capacitance at the node when the switch is open. Since the voltage of the node remains substantially unchanged after the switch opens, the current from the current source need not substantially charge or discharge this inherent capacitance when the switch subsequently closes in order to permit a transistor of the emitter-coupled pair to turn on.